Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity cnter4 is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end cnter_4;
architecture cnter_4_arc of cnter_4 is
begin
counting : process (clk,reset) is
variable m : std_logic_vector (3 downto 0) := "0000";
begin
if (reset='1') then
m := "0000";
elsif (rising_edge (clk)) then
m := m + 1;
end if;
dout <= m;
end process counting;
end cnter_4_arc;